parent
a35f6a8dbb
commit
ec2d8d5eeb
@ -0,0 +1,55 @@
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# Calculate format=diff pkg(sys-kernel/calculate-sources)>=4.2&&pkg(sys-kernel/calculate-sources)<4.3&&merge(x11-drivers/ati-drivers)==15.9-r1&&os_arch_machine==i686
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diff --git a/common/lib/modules/fglrx/build_mod/firegl_public.c b/common/lib/modules/fglrx/build_mod/firegl_public.c
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index 677565d..5189bd4 100755
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--- a/common/lib/modules/fglrx/build_mod/firegl_public.c
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+++ b/common/lib/modules/fglrx/build_mod/firegl_public.c
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@@ -258,23 +258,6 @@
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#define __flush_tlb_one(addr) asm volatile("invlpg (%0)" ::"r" (addr) : "memory")
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#define __flush_tlb() native_write_cr3(native_read_cr3())
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-static inline void __flush_tlb_all(void)
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-{
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- if (cpu_has_pge)
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- {
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- unsigned long flags, cr4;
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- raw_local_irq_save(flags);
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- cr4 = native_read_cr4();
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- native_write_cr4(cr4 & ~X86_CR4_PGE);
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- native_write_cr4(cr4);
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- raw_local_irq_restore(flags);
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- }
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- else
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- {
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- __flush_tlb();
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- }
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-}
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-
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// ============================================================
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/* globals */
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@@ -6436,21 +6436,17 @@ static int KCL_fpu_save_init(struct task_struct *tsk)
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struct fpu *fpu = &tsk->thread.fpu;
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if(static_cpu_has(X86_FEATURE_XSAVE)) {
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- fpu_xsave(fpu);
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- if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
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+ copy_xregs_to_kernel(&fpu->state.xsave);
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+ if (!(fpu->state.xsave.header.xfeatures & XSTATE_FP))
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return 1;
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} else if (static_cpu_has(X86_FEATURE_FXSR)) {
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- fpu_fxsave(fpu);
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+ copy_fxregs_to_kernel(fpu);
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} else {
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asm volatile("fnsave %[fx]; fwait"
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- : [fx] "=m" (fpu->state->fsave));
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+ : [fx] "=m" (fpu->state.fsave));
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return 0;
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}
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- if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) {
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- asm volatile("fnclex");
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- return 0;
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- }
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return 1;
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}
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#endif
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