25 lines
904 B
XML
25 lines
904 B
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE pkgmetadata SYSTEM "http://www.gentoo.org/dtd/metadata.dtd">
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<pkgmetadata>
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<maintainer type="person">
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<email>vowstar@gmail.com</email>
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<name>Huang Rui</name>
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</maintainer>
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<maintainer type="project">
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<email>sci-electronics@gentoo.org</email>
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<name>Gentoo Electronics Project</name>
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</maintainer>
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<maintainer type="project">
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<email>proxy-maint@gentoo.org</email>
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<name>Proxy Maintainers</name>
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</maintainer>
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<upstream>
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<remote-id type="github">steveicarus/iverilog</remote-id>
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</upstream>
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<longdescription>
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Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
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compiler, compiling source code writen in Verilog (IEEE-1364) into some target
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format. The compiler proper is intended to parse and elaborate design
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descriptions written to the IEEE standard IEEE Std 1364-2001.
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</longdescription>
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</pkgmetadata>
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