You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
14 lines
800 B
14 lines
800 B
DEFINED_PHASES=install prepare
|
|
DEPEND=app-arch/bzip2 sys-libs/readline sys-libs/zlib
|
|
DESCRIPTION=A Verilog simulation and synthesis tool
|
|
EAPI=4
|
|
HOMEPAGE=http://iverilog.icarus.com/
|
|
IUSE=examples
|
|
KEYWORDS=amd64 ppc sparc x86
|
|
LICENSE=GPL-2
|
|
RDEPEND=app-arch/bzip2 sys-libs/readline sys-libs/zlib
|
|
SLOT=0
|
|
SRC_URI=ftp://icarus.com/pub/eda/verilog/v0.9/verilog-0.9.6.tar.gz
|
|
_eclasses_=desktop 2ccd1dd1dd7bfb8795eea024a4f91bb6 epatch 9a5f039771f143195164a15a4faa41a1 estack 43ddf5aaffa7a8d0482df54d25a66a1f eutils 63392afb034aad67f17fa129019eb4d9 ltprune 607e058da37aa6dabfa408b7d61da72e multilib 97f470f374f2e94ccab04a2fb21d811e preserve-libs ef207dc62baddfddfd39a164d9797648 toolchain-funcs 1e35303c63cd707f6c3422b4493d5607 vcs-clean 2a0f74a496fa2b1552c4f3398258b7bf
|
|
_md5_=6c390db9e7a005dbbc244949cbec6e42
|