You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
gentoo-overlay/metadata/md5-cache/sci-electronics/iverilog-9999

14 lines
922 B

BDEPEND=dev-util/gperf app-alternatives/yacc app-alternatives/lex >=app-portage/elt-patches-20240116 sys-devel/gnuconfig || ( >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7-r3 >=dev-vcs/git-1.8.2.1[curl]
DEFINED_PHASES=install prepare unpack
DEPEND=sys-libs/readline:= sys-libs/zlib
DESCRIPTION=A Verilog simulation and synthesis tool
EAPI=8
HOMEPAGE=http://iverilog.icarus.com https://github.com/steveicarus/iverilog
INHERIT=autotools git-r3
LICENSE=LGPL-2.1
PROPERTIES=live
RDEPEND=sys-libs/readline:= sys-libs/zlib
SLOT=0
_eclasses_=autotools dc70c1dc473b68317fc4a86f5fbfc57d git-r3 fbb2889c81f3a05910c1524db69425c1 gnuconfig a397adda6984a4c423e28ac274c1ba98 libtool 5f49a16f67f81bdf873e3d1f10b10001 multilib c19072c3cd7ac5cb21de013f7e9832e0 toolchain-funcs e56c7649b804f051623c8bc1a1c44084
_md5_=3e1df22ca7238532a27bb8246507e22b